1. Field of the Invention
This invention generally relates to a semiconductor device, a mask for impurity implantation, and a method of fabricating the semiconductor device, and more particularly, to techniques that enable the semiconductor device to have a higher breakdown voltage.
2. Description of the Related Art
A device structure having an offset region arranged between a gate electrode and a drain electrode is well known so that the semiconductor device has a higher breakdown voltage.
FIG. 1A is a schematic cross-sectional view of a conventional laterally diffused MOS (hereinafter referred to as LDMOS) transistor having a single offset region. The LDMOS transistor is a MOSFET having a high breakdown voltage, and is widely used for operating at frequencies as high as several GHz. In the LDMOS transistor, an impurity is diffused or implanted in a channel region provided under the gate electrode by laterally diffusing from a source region to a drain region. Thus, the region under the gate electrode has an impurity distribution in which a portion of the region close to the source region is relatively high and another portion close to the drain region is relatively low.
Referring to FIG. 1A, a reference numeral 11 denotes a heavily doped (P++) substrate. A reference numeral 12 denotes a p-type epitaxial layer, which is epitaxially grown on a main surface of the substrate 11. A reference numeral 17 denotes a gate oxide film. A reference numeral 18 denotes a gate electrode. A surface region of the p-type epitaxial layer 12 includes a channel region 13 (P), an offset region 14 (N), a drain region 15 (N++), and a source region 16 (N++). The offset region 14 is arranged between the gate electrode 18 and a drain electrode (not shown), and thereby the distance between the gate electrode 18 and the drain electrode is longer than that between the gate electrode 18 and a source electrode (not shown). In other words, the source electrode and the drain electrode are arranged asymmetrically with respect to the gate electrode. The aforementioned electrode structure is generally referred to as an offset gate electrode structure. Generally, the offset region 14 is designed to be long in order to realize a high drain breakdown voltage.
FIG. 1B shows a profile of an n-type impurity concentration in the offset region of the LDMOS transistor shown in FIG. 1A. Here, a donor concentration is uniformly distributed in the whole offset region ranging from an edge of the gate to an edge of the drain. The impurity concentration significantly changes at the edge of the gate interfaced with a P channel region. The impurity concentration drastically changes at the edge of the drain interfaced with the N++ drain region.
FIG. 1C shows a field intensity distribution in the offset region having the above-mentioned impurity profile. As shown in FIG. 1C, the peaks of the electric field intensity appear on an edge of a channel region and an edge of a drain region in the offset region, those steep peaks making it difficult to realize a higher drain breakdown voltage.
The above-mentioned steep peaks are caused due to the drastic changes in the impurity concentrations in interfaces between the offset region and the channel region and between the offset region and the drain region. That is to say, when the impurity concentration significantly changes, the energy band steeply bends according to the difference in the Fermi level between the adjacent regions, and the electric potential greatly changes, so that the peaks appear in the distribution of the electric field intensity. The existence of the peaks in the electric field intensity has to lengthen the offset region more than necessary in order to obtain a given drain breakdown voltage. It is thus difficult to reduce the on-state resistance and parasitic capacitance.
Japanese Patent Application Publication No. 7-211917 (hereinafter referred to as Document 1) discloses a semiconductor device that suppresses the peaks of the electric field near the channel region and the drain region in the offset region to equalize the electric field in the offset region, and achieves the given drain breakdown voltage in the offset gate region having a short length, in order to reduce the on-resistance and parasitic capacitance.
FIG. 2A is a schematic cross-sectional view of the LDMOS transistor having a normal offset region other than an SOI structure, to divide the impurity concentration of the offset region described in Document 1 into two regions having different impurity concentrations. Referring to FIG. 2A, a reference numeral 21 denotes a heavily doped (P++) substrate. A reference numeral 22 denotes a p-type epitaxial layer, which is epitaxially grown on a main surface of the substrate 21. A reference numeral 27 denotes a gate oxide film. A reference numeral 28 denotes a gate electrode. A surface region of the p-type epitaxial layer 22 includes a channel region 23 (P), and an offset region 24 (N), a drain region 25 (N++), and a source region 26 (N++). The offset region 24 includes two regions having different impurity concentrations, a first offset region 24a and a second offset region 24b. 
FIG. 2B shows a profile of an n-type impurity concentration in the surface region of the offset region in the LDMOS transistor shown in FIG. 2A. The distributions of the donor concentrations are respectively equalized in both the first offset region 24a extending from the gate edge and the second offset region 24b extending from the edge of the drain. At the interface between the two regions, the impurity concentrations change in a discontinuous manner.
When the impurity concentration distribution in FIG. 2B is compared with that of FIG. 1B, the impurity concentration drastically changes at the edge of the drain region, that is, the interface with the N++ drain region, which is same as FIG. 1B. However, the donor concentrations of the first offset region 24a and the second offset region 24b can reduce the change of the impurity concentrations at the edge of the gate interfaced with the P channel region 23.
FIG. 2C shows the electric field intensity distribution in the offset region having the above-mentioned impurity profile. As shown in FIG. 2C, another peak appears in the interface between the first offset region 24a and the second offset region 24b caused resulting from the change of the donor concentration. The existing peaks become lower at the edges in the offset region. This is reflected by a reduction in the change in the impurity concentration at the edge of the gate in the offset region interfaced with the P channel region. The difference in the impurity concentrations is reduced by providing the first offset region 24a and the second offset region 24b having the different donor concentrations. As a whole, the electric field intensity becomes lower and the higher breakdown voltage is obtainable.
FIGS. 3A through 3G illustrate a process of fabricating the LDMOS transistor shown in FIG. 2A. Referring to FIG. 3A, first, the p-type epitaxial layer 22 is grown on the main surface of the heavily doped (P++) substrate 21. Referring to FIG. 3B, the gate oxide film 27 and the gate electrode 28 are formed on the p-type epitaxial layer 22. Next, referring to FIG. 3C, an impurity serving as an acceptor is partially ion-implanted in the p-type epitaxial layer 22 to form the p-type channel region 23. Referring to FIG. 3D, an impurity serving as a donor is ion-implanted to form the first n-type offset region 24a. 
Then, referring to a top view of FIG. 3E, a photoresist 29 is provided to partially expose the first offset region 24a. Referring to FIG. 3F, an impurity serving as a donor is ion-implanted to form the second n-type offset region 24b. Finally, referring to FIG. 3G, a photoresist (not shown) is provided for a mask to partially expose the second n-type offset region 24b and the p-type channel region 23, an impurity serving as a donor is ion-implanted shallowly to form the drain region 25 (N++) and the source region 26 (N++).
The offset region disclosed in Document 1, however, includes the first and second offset regions, which are respectively and independently formed. The ion-implantation is performed twice to ion-implant two different donor concentrations. This increases the number of production steps and the production cost.
Japanese Patent Application Publication No. 5-304169 (hereinafter referred to as Document 2) describes a fabricating method of the semiconductor device having two ion-implantation layers having two different impurity concentrations so as to eliminate a masking process. Specifically, two openings having different sizes are arranged in a photoresist serving as a mask for ion-implantation. Ions are implanted through a small opening at an angle at which the semiconductor substrate is not exposed. Then, ions are implanted through the small opening at another angle at which the semiconductor substrate is exposed. Thus, with the once-performed time photolithography process, two different diffusion layers having different concentration distributions are formed in given regions. Japanese Patent Application Publication No. 2003-152095 (hereinafter referred to as Document 3) discloses a fabricating method of an IC having a high breakdown voltage at a low cost. This method forms a first well region and a second well region with a sheet of photo mask and once-performed ion-implantation.
In order to satisfy the demands for the higher breakdown voltage on the semiconductor device, it is not sufficient to realize multiple concentration distributions in the offset region only. The impurity concentration distribution is demanded to realize a mild bending of the energy band. Therefore, the impurity concentration distribution is required to design to realize the higher breakdown voltage, taking into consideration of parameters comprehensively such as thermal treatment temperature in the device fabrication process, time-varying diffusion length of the impurity, and spatial range of the offset region. In addition, it is also demanded that the impurity concentration distribution can be designed freely according to device characteristics.